Some circuits used for internal test mode are provided in the semiconductor memory circuit design. These circuits are transparent to users and may never be used in normal applications. However, the circuits can be used to adjust the internal circuit timing and internal voltages, to change the internal control logic, or for other specific purposes. In consideration of the usages of the test circuits, they are required to have the following two features: firstly, the test circuits should not enter into the test mode during users' normal (valid) operations; secondly, the test circuits should be capable of entering into the test mode during the product development and test procedures. Therefore, it is usual to use extra pins to input and output signals of the test circuit, which are grounded (i.e. in the disabled state) during the normal operations. Sometimes, a specific section of code is added into a clock signal for the chip to control the test circuit, and the users are restricted from using the section of code as defined in the product datasheet.
Regarding an ASRAM product, the aforementioned method can not be used due to some specific features of the ASRAM product. Firstly, the ASRAM is a generic product having a common package, i.e. products from different companies use exactly the same package, thus no extra pins can be used for the test mode. Secondly, the ASRAM operates in an asynchronous manner, therefore it does not have an external clock. Thirdly, there are various applications of the ASRAM, it is improper to restrict the users from using a specific section of code in the product datasheet, otherwise the compatibility of the generic ASRAM product may be adversely affected.
Therefore, a previously used method for control the test mode entry of the ASRAM product is to apply a super-high input high (SVIH) voltage at one or more pins of the ASRAM product and maintain the SVIH voltage for a period of time to trigger its internal test circuit. The term SVIH indicates a voltage being an extra value higher than the supply voltage. For example, for a 3.3V ASRAM, the SVIH voltage of 3.3V+0.7V is applied at the pins thereof. Under normal conditions, the pins of the ASRAM will not be applied of any voltage higher than the supply voltage Vcc of the ASRAM, and the voltage Vih (the input high voltage applied at the pins) defined in the datasheet is lower than or equal to the supply voltage Vcc. The purpose of maintaining the SVIH voltage for a period of time (for example, 100 ns) is to avoid incorrectly triggering the test circuit due to some glitches at the pins.
Although the method works, it still has some drawbacks. Firstly, the voltages at some pins are required to be higher than the supply voltage Vcc. An Electro-Static Discharge (ESD) protection circuit is generally coupled to the pins, which may comprise a pair of reversely biased diodes. When the voltage at the pins is higher than the supply voltage Vcc, the diodes may be turned on to generate a current flowing from the pins to the supply voltage Vcc. Secondly, during the design of the circuit, the SVIH voltage may sometimes be designed a bit higher, such as Vcc+1.5V, to provide some design margin and to enable the circuit to operate under a low supply voltage. However, during the actual test procedures, because of the deviations of the chips and the working conditions, such as deviations of the process/voltage/temperature (PVT), the test platform may apply a much higher SVIH voltage to ensure that every tested chip enters into the test mode. For example, the SVIH voltage may be 6V when the supply voltage Vcc is 4V. Such high SVIH voltage is close to the breakdown voltage of the transistors manufactured in some processes, which is extremely harmful to the chips. Thirdly, it is generally required to perform some complicated function test to the ASRAM when the ASRAM enters into and remains in some test mode. The Vih configuration of the pins can not be changed in line in some old test platforms, or the old test platforms cannot provide several different groups of Vih configurations.